Five Minute VHDL Podcast

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Let's talk about hardware design using VHDL

Francesco Richichi


    • May 18, 2019 LATEST EPISODE
    • infrequent NEW EPISODES
    • 5m AVG DURATION
    • 33 EPISODES


    Search for episodes from Five Minute VHDL Podcast with a specific topic:

    Latest episodes from Five Minute VHDL Podcast

    Q&A#10 RAM Parallelism

    Play Episode Listen Later May 18, 2019 3:40


    How I can parallelize a RAM in FPGAhttps://surf-vhdl.com/how-to-implement-a-multi-port-memory-on-fpga/Websitehttps://surf-vhdl.comTelegram channelhttps://t.me/SurfVhdlYou can contact memail: podcast@surf-vhdl.comTelegram: https://t.me/francesco_surfvhdlTeachable courseshttps://surf-vhdl.link/courses

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    ep#22-Multiplier optimization

    Play Episode Listen Later May 13, 2019 5:23


    Learn how to optimize a multiplier in particular cases:For a technical analysis go to the post:https://surf-vhdl.link/OptimizationVhdl12b25Websitehttps://surf-vhdl.comTelegram channelhttps://t.me/SurfVhdlYou can contact memail: podcast@surf-vhdl.comTelegram: https://t.me/francesco_surfvhdlTeachable courseshttps://surf-vhdl.link/courses

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    Ep#21-Serial-to-Parallel Parallel-to-Serial converter

    Play Episode Listen Later Apr 28, 2019 7:24


    Link to the post:https://surf-vhdl.link/99990Websitehttps://surf-vhdl.comTelegram channelhttps://t.me/SurfVhdlYou can contact memail: podcast@surf-vhdl.comTelegram: https://t.me/francesco_surfvhdlTeachable courseshttps://surf-vhdl.link/coursesMusic by Francis Preve - https://www.francispreve.com

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    Q&A#09-I need a clock!

    Play Episode Listen Later Apr 23, 2019 9:01


    In this podcast we will understand how to connect a clock signal to our FPGAWebsitehttps://surf-vhdl.comTelegram channelhttps://t.me/SurfVhdlYou can contact memail: podcast@surf-vhdl.comTelegram: https://t.me/francesco_surfvhdlTeachable courseshttps://surf-vhdl.link/courses

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    Q&A#08- What is the dithering

    Play Episode Listen Later Apr 10, 2019 4:30


    What is dithering? Where we can use this technique?Websitehttps://surf-vhdl.comTelegram channelhttps://t.me/SurfVhdlYou can contact memail: podcast@surf-vhdl.comTelegram: https://t.me/francesco_surfvhdlTeachable courseshttps://surf-vhdl.link/coursesMusic by Francis Preve - https://www.francispreve.com

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    ep#20-VHDL Generic

    Play Episode Listen Later Apr 6, 2019 5:34


    VHDL GenericWebsitehttps://surf-vhdl.comTelegram channelhttps://t.me/SurfVhdlYou can contact memail: podcast@surf-vhdl.comTelegram: https://t.me/francesco_surfvhdlTeachable courseshttps://surf-vhdl.link/coursesMusic by Francis Preve - https://www.francispreve.com

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    Ep#19-Iterative statement

    Play Episode Listen Later Mar 22, 2019 4:43


    Even if the VHDL is not a software language, we can find a tyoica SW statement, the iterative statement. Let’s see how to use thishttps://t.me/SurfVhdl/92Websitehttps://surf-vhdl.comTelegram channelhttps://t.me/SurfVhdlYou can contact memail: podcast@surf-vhdl.comTelegram: https://t.me/francesco_surfvhdlTeachable courseshttps://surf-vhdl.link/coursesMusic by Francis Preve - https://www.francispreve.com

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    Ep#18-the conditional assignment in VHDL

    Play Episode Listen Later Mar 18, 2019 7:28


    Let’s understand how to implement a conditional statement in VHDLimage for the episodehttp://t.me/SurfVhdl/86Websitehttps://surf-vhdl.comTelegram channelhttps://t.me/SurfVhdlYou can contact memail: podcast@surf-vhdl.comTelegram: https://t.me/francesco_surfvhdlTeachable courseshttps://surf-vhdl.link/coursesMusic by Francis Preve - https://www.francispreve.com

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    ep#17-wait

    Play Episode Listen Later Mar 13, 2019 5:22


    Wait Statements in VHDLReference to pictures:https://t.me/SurfVhdl/82Websitehttps://surf-vhdl.comTelegram channelhttps://t.me/SurfVhdlYou can contact memail: podcast@surf-vhdl.comTelegram: https://t.me/francesco_surfvhdlTeachable courseshttps://surf-vhdl.link/coursesMusic by Francis Preve - https://www.francispreve.com

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    Q&A#07- What is the first thing that a recruiter does?

    Play Episode Listen Later Mar 7, 2019 4:04


    Q&A#07- What is the first thing that a recruiter does?When a recruiter needs to hire you as VHDL expert, what do you think he or she will do to understand if you are good for him or her?What can you do in order to result a VHDL user?Let’s see in this podcast.Here you can find the feedback of my VHDL student https://surf-vhdl.link/vhdl-studentTelegram channelhttps://t.me/SurfVhdlYou can contact memail: podcast@surf-vhdl.comTelegram: https://t.me/francesco_surfvhdlTeachable courseshttps://surf-vhdl.link/courses

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    Ep#16-VHDL process

    Play Episode Listen Later Mar 6, 2019 7:17


    And now is time to introduce formally a Processlink to the imageshttps://t.me/SurfVhdl/78Websitehttps://surf-vhdl.comTelegram channelhttps://t.me/SurfVhdlYou can contact memail: podcast@surf-vhdl.comTelegram: https://t.me/francesco_surfvhdlTeachable courseshttps://surf-vhdl.link/coursesMusic by Francis Preve - https://www.francispreve.com

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    Q&A#06- How can I generate a new clock from a reference clock?

    Play Episode Listen Later Mar 1, 2019 10:38


    I receiver a question from Sandip. He got my reference, from my post on DDS.The question is:“I want to generate Square of 999kHz, 1000kHz and 1001kHzin VHDL Language and that would be implemented on a Zynq ZC702 evaluation board.Is it possible by using the DDS.? Can you provide your expertise and comment on it.”Websitehttps://surf-vhdl.comTelegram channelhttps://t.me/SurfVhdlYou can contact memail: podcast@surf-vhdl.comTelegram: https://t.me/francesco_surfvhdlTeachable courseshttps://surf-vhdl.link/coursesMusic by Francis Preve - https://www.francispreve.com

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    Ep#15-VHDL Packages

    Play Episode Listen Later Feb 14, 2019 3:51


    VHDL Packageshttp://t.me/SurfVhdl/74Websitehttps://surf-vhdl.comTelegram channelhttps://t.me/SurfVhdlYou can contact memail: podcast@surf-vhdl.comTelegram: https://t.me/francesco_surfvhdlTeachable courseshttps://surf-vhdl.link/coursesMusic by Francis Preve - https://www.francispreve.com

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    Ep#14-VHDL object

    Play Episode Listen Later Feb 11, 2019 6:11


    After signal introduction, let's view what are the remaining VHDL objectsImages https://t.me/SurfVhdl/72Websitehttps://surf-vhdl.comTelegram channelhttps://t.me/SurfVhdlYou can contact memail: podcast@surf-vhdl.comTelegram: https://t.me/francesco_surfvhdlTeachable courseshttps://surf-vhdl.link/coursesMusic by Francis Preve - https://www.francispreve.com

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    Q&A#05- Does the USB transfer work as UART?

    Play Episode Listen Later Feb 10, 2019 9:15


    I received a question from Haitham. He have to connect a computer to an FPGA using USB connection in order to transfer data from FPGA to the PC. Haitham is following my VHDL course “Start Learning VHDL Using FPGA”. In this course the last LAB implement communication between PC and FPGA using UART channel.After starting the course, Haitham asked me: “Does the USB transfer work as UART”?Let’s see the answer. Here the link to the picture on the telegram channelhttps://t.me/SurfVhdl/68Websitehttps://surf-vhdl.comTelegram channelhttps://t.me/SurfVhdlYou can contact memail: podcast@surf-vhdl.comTelegram: https://t.me/francesco_surfvhdlTeachable courseshttps://surf-vhdl.link/coursesMusic by Francis Preve - https://www.francispreve.com

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    QA#04-What is the VHDL design flow

    Play Episode Listen Later Feb 8, 2019 7:09


    In this Q&A episode I want to answer to the question on what is the VHLD design flowTo better follow the episode, see the picture on the telegram channelhttps://t.me/SurfVhdl/65Websitehttps://surf-vhdl.comTelegram channelhttps://t.me/SurfVhdlYou can contact memail: podcast@surf-vhdl.comTelegram: https://t.me/francesco_surfvhdlTeachable courseshttps://surf-vhdl.link/coursesMusic by Francis Preve - https://www.francispreve.com

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    Ep#13-a way to remember-the flip-flop

    Play Episode Listen Later Feb 7, 2019 5:41


    Introducing Flip-Flop in VHDLLink to the picture in the telegram channelhttps://t.me/SurfVhdl/61Websitehttps://surf-vhdl.comTelegram channelhttps://t.me/SurfVhdlYou can contact memail: podcast@surf-vhdl.comTelegram: https://t.me/francesco_surfvhdlTeachable courseshttps://surf-vhdl.link/coursesMusic by Francis Preve - https://www.francispreve.com

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    QA#3-plzz send the test bench

    Play Episode Listen Later Feb 5, 2019 3:40


    This is the question many of you ask me very oftenI wish to give you some hint and a test bench template I use in my VHDL designs Here the link to the test bench template: https://t.me/SurfVhdl/58Websitehttps://surf-vhdl.comTelegram channelhttps://t.me/SurfVhdlYou can contact memail: podcast@surf-vhdl.comTelegram: https://t.me/francesco_surfvhdlTeachable courseshttps://surf-vhdl.link/coursesMusic by Francis Preve - https://www.francispreve.com

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    Ep#12-VHDL Simulation

    Play Episode Listen Later Feb 3, 2019 5:51


    A brief overview to setup a ModelSim simulation environmentLink to the episode#12 picturet.me/SurfVhdl/53Websitehttps://surf-vhdl.comTelegram channelhttps://t.me/SurfVhdlYou can contact memail: podcast@surf-vhdl.comTelegram: https://t.me/francesco_surfvhdlTeachable courseshttps://surf-vhdl.link/coursesMusic by Francis Preve - https://www.francispreve.com

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    Ep#11-what is a signal

    Play Episode Listen Later Feb 1, 2019 3:53


    Introduce signal in VHDL, what is a signal and how to use it.Image relative to this episodeWebsitehttps://surf-vhdl.comTelegram channelhttps://t.me/SurfVhdlYou can contact memail: podcast@surf-vhdl.comTelegram: https://t.me/francesco_surfvhdlTeachable courseshttps://surf-vhdl.link/coursesMusic by Francis Preve - https://www.francispreve.com

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    Ep#10-More on driver the resolution function

    Play Episode Listen Later Jan 30, 2019 8:13


    Solving a dispute in VHDL: the resolution functionLink to image for the episode#10Solving a dispute in VHDL: the resolution functiont.me/SurfVhdl/50Websitehttps://surf-vhdl.comTelegram channelhttps://t.me/SurfVhdlYou can contact memail: podcast@surf-vhdl.comTelegram: https://t.me/francesco_surfvhdlTeachable courseshttps://surf-vhdl.link/coursesMusic by Francis Preve - https://www.francispreve.com

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    Ep#09-What is a driver in VHDL

    Play Episode Listen Later Jan 29, 2019 3:57


    What is a driver in VHDL?Images for the episodet.me/SurfVhdl/46Websitehttps://surf-vhdl.comTelegram channelhttps://t.me/SurfVhdlYou can contact memail: podcast@surf-vhdl.comTelegram: https://t.me/francesco_surfvhdlTeachable courseshttps://surf-vhdl.link/coursesMusic by Francis Preve - https://www.francispreve.com

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    QA#2-SPI-controller-simulation with Vivado

    Play Episode Listen Later Jan 28, 2019 2:03


    In this brief episode I want to answer a question from Klajdi on simulation of SPI controller using Vivado Websitehttps://surf-vhdl.comTelegram channelhttps://t.me/SurfVhdlYou can contact memail: podcast@surf-vhdl.comTelegram: https://t.me/francesco_surfvhdlTeachable courseshttps://surf-vhdl.link/courses

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    QA#1-Do we need clock and address

    Play Episode Listen Later Jan 26, 2019 3:55


    Answering to Prashant. He asked me this question “What do we have to give as an input for i_clk and i_addr?”relative to the post: https://surf-vhdl.com/how-to-generate-sine-samples-in-vhdl/Websitehttps://surf-vhdl.comTelegram channelhttps://t.me/SurfVhdlYou can contact memail: podcast@surf-vhdl.comTelegram: https://t.me/francesco_surfvhdlTeachable courseshttps://surf-vhdl.link/coursesMusic by Francis Preve - https://www.francispreve.com/

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    Ep#08-concurrency

    Play Episode Listen Later Jan 25, 2019 6:36


    In this episode we will introduce the Concurrency conceptWebsitehttps://surf-vhdl.comTelegram channelhttps://t.me/SurfVhdlYou can contact memail: podcast@surf-vhdl.comTelegram: https://t.me/francesco_surfvhdlTeachable courseshttps://surf-vhdl.link/coursesMusic by Francis Preve - https://www.francispreve.com

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    Ep#07-introducing the entity

    Play Episode Listen Later Jan 22, 2019 9:53


    Introducing Entity. The basic building VHDL blockWebsitehttps://surf-vhdl.comTelegram channelhttps://t.me/SurfVhdlYou can contact memail: podcast@surf-vhdl.comTelegram: https://t.me/francesco_surfvhdlTeachable courseshttps://surf-vhdl.link/coursesMusic by Francis Preve - https://www.francispreve.com

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    Ep#06-Ok, and now how do I test it?

    Play Episode Listen Later Jan 19, 2019 4:36


    Let’s understand how digital electronics help us in the debug and test of our designWebsitehttps://surf-vhdl.comTelegram channelhttps://t.me/SurfVhdlYou can contact memail: podcast@surf-vhdl.comTelegram: https://t.me/francesco_surfvhdlTeachable courseshttps://surf-vhdl.link/coursesMusic by Francis Preve - https://www.francispreve.com

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    Ep#05-male and female logic

    Play Episode Listen Later Jan 18, 2019 4:17


    Learn how men and women can be identified as digital circuitsWebsitehttps://surf-vhdl.comTelegram channelhttps://t.me/SurfVhdlYou can contact memail: podcast@surf-vhdl.comTelegram: https://t.me/francesco_surfvhdlTeachable courseshttps://surf-vhdl.link/coursesMusic by Francis Preve - https://www.francispreve.com/

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    EP#04-Two is enough

    Play Episode Listen Later Jan 15, 2019 6:26


    Why do we use only two logic level in digital design?Figures:https://t.me/SurfVhdl/32Websitehttps://surf-vhdl.comTelegram channelhttps://t.me/SurfVhdlYou can contact memail: podcast@surf-vhdl.comTelegram: https://t.me/francesco_surfvhdlTeachable courseshttps://surf-vhdl.link/coursesMusic by Francis Preve - https://www.francispreve.com

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    Ep#03-a really important thing the interfaces

    Play Episode Listen Later Jan 15, 2019 4:41


    Let's introduce the FLAT and Hierarchical methodology in Hardware DesignWebsitehttps://surf-vhdl.comTelegram channelhttps://t.me/SurfVhdlYou can contact memail: podcast@surf-vhdl.comTelegram: https://t.me/francesco_surfvhdlTeachable courseshttps://surf-vhdl.link/coursesMusic by Francis Preve - https://www.francispreve.com

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    Ep#02-the three secrets that no hardware designer will ever tell you

    Play Episode Listen Later Jan 14, 2019 5:09


    Start understanding few rules for a good VHDL design habitsWebsitehttps://surf-vhdl.comTelegram channelhttps://t.me/SurfVhdlYou can contact memail: podcast@surf-vhdl.comTelegram: https://t.me/francesco_surfvhdlTeachable courseshttps://surf-vhdl.link/coursesMusic by Francis Preve - https://www.francispreve.com

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    Ep#01-Why you should learn VHDL

    Play Episode Listen Later Jan 13, 2019 5:21


    Do you like digital electronic? Why you should learn VHDL? Let's understand in this episodeWebsitehttps://surf-vhdl.comTelegram channelhttps://t.me/SurfVhdlYou can contact memail: podcast@surf-vhdl.comTelegram: https://t.me/francesco_surfvhdlTeachable courseshttps://surf-vhdl.link/coursesMusic by Francis Preve - https://www.francispreve.com

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    Ep#0-why a podcast on VHDL

    Play Episode Listen Later Jan 12, 2019 4:41


    Episode zero to introduce the Surf-VHDL Podcast:Five Minute VHDLWebsitehttps://surf-vhdl.comTelegram channelhttps://t.me/SurfVhdlYou can contact memail: podcast@surf-vhdl.comTelegram: https://t.me/francesco_surfvhdlTeachable courseshttps://surf-vhdl.link/cousesMusic by Francis Preve - https://www.francispreve.com/

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