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Thrilled to have Crow Moon back again today to chat about so many topics including updates to his practice in the last year, teaching Living a Wiccan Life, creating folk music and witchy poetry (listen for the original Litha poem shared!), tips for beginner Wiccans and artists, and generally living in accordance with seasons and the Wheel of the Year.Find Crow Moon:Website: Crowmoonaz.comInstagram: @crowmoon5Meditations and Courses: https://insighttimer.com/crowmoon/coursesMusic: https://open.spotify.com/artist/2RLlU7E1aRRb1Uxy1m6sT3Crow Moon is the founder of the Corvidae Circle Wiccan Tradition. He teaches Wicca, nature-based spirituality, and meditation online. Crow Moon is also a musician and produces witchy, folk-inspired music.
Steve Hsu, Richard Hanania, and Rob Henderson were scheduled for a June 2023 panel as part of the University of Austin (UATX) Forbidden Courses series. Steve missed the panel due to travel issues, but the three have gathered on this podcast to recreate the fun!They discuss:0:00 Introduction1:20 The University of Austin and forbidden courses17:37 Will woke campus culture change anytime soon?29:57 Common people vs elites on affirmative action35:42 Why it's uncomfortable to disagree about affirmative action41:22 Fraud and misrepresentation in higher ed44:20 The adversity carveout in the Supreme Court affirmative action ruling50:10 Standardized testing and elite university admissions1:06:18 Divergent views among racial and ethnic groups on affirmative action; radicalized Asian American males1:10:00 Differences between East and South Asians in the West 1:23:03 Class-based preferences and standardized tests1:31:57 Rob Henderson's next move LINKSRichard Hanania's new book: The Origins of Woke: Civil Rights Law, Corporate America, and the Triumph of Identity Politics: https://www.harpercollins.com/products/the-origins-of-woke-richard-hanania?variant=41004650528802Richard Hanania's newsletter: https://www.richardhanania.com/The Center for the Study of Partisanship and Ideology: https://www.cspicenter.com/Rob Henderson's newsletter: https://www.robkhenderson.com/Rob Henderson's new book: Troubled: A Memoir of Foster Care, Family, and Social Class: https://www.simonandschuster.com/books/Troubled/Rob-Henderson/9781982168537UATX: https://www.uaustin.org/forbidden-coursesMusic used with permission from Blade Runner Blues Livestream improvisation by State Azure.--Steve Hsu is Professor of Theoretical Physics and of Computational Mathematics, Science, and Engineering at Michigan State University. Previously, he was Senior Vice President for Research and Innovation at MSU and Director of the Institute of Theoretical Science at the University of Oregon. Hsu is a startup founder (SafeWeb, Genomic Prediction, Othram) and advisor to venture capital and other investment firms. He was educated at Caltech and Berkeley, was a Harvard Junior Fellow, and has held faculty positions at Yale, the University of Oregon, and MSU.Please send any questions or suggestions to manifold1podcast@gmail.com or Steve on Twitter @hsu_steve.
Edible Gardens are an important topic in the landscape. From seed to harvest, much goes into the placing and planning of a successful edible garden. Hosts Charles and Kate Sadler discuss design considerations and planting suggestions for success.For more, visit www.kinggardeninc.com/in-the-landscape for full show notes, links to additional resources, transcripts of episodes, host bios and more! For courses that go more in depth on landscape topics, visit: https://kinggardeninc.com/online-coursesMusic: https://www.purple-planet.com
Link to the post:https://surf-vhdl.link/99990Websitehttps://surf-vhdl.comTelegram channelhttps://t.me/SurfVhdlYou can contact memail: podcast@surf-vhdl.comTelegram: https://t.me/francesco_surfvhdlTeachable courseshttps://surf-vhdl.link/coursesMusic by Francis Preve - https://www.francispreve.com
In questo episodio scopriamo cosa è il dithering e quando possiamo utilizzare questa tecnica.Websitehttps://surf-vhdl.comTelegram channelhttps://t.me/SurfVhdlYou can contact memail: podcast@surf-vhdl.comTelegram: https://t.me/francesco_surfvhdlTeachable courseshttps://surf-vhdl.link/coursesMusic by Francis Preve - https://www.francispreve.com
What is dithering? Where we can use this technique?Websitehttps://surf-vhdl.comTelegram channelhttps://t.me/SurfVhdlYou can contact memail: podcast@surf-vhdl.comTelegram: https://t.me/francesco_surfvhdlTeachable courseshttps://surf-vhdl.link/coursesMusic by Francis Preve - https://www.francispreve.com
VHDL GenericWebsitehttps://surf-vhdl.comTelegram channelhttps://t.me/SurfVhdlYou can contact memail: podcast@surf-vhdl.comTelegram: https://t.me/francesco_surfvhdlTeachable courseshttps://surf-vhdl.link/coursesMusic by Francis Preve - https://www.francispreve.com
Finalmente l'ho capito anche io.In questa puntata voglio svelare il segreto del perché si utilizza il VHDL.Scopriamolo insieme ad un ospite specialeWebsitehttps://surf-vhdl.comTelegram channelhttps://t.me/SurfVHDLPodcastYou can contact memail: podcast@surf-vhdl.comTelegram: https://t.me/francesco_surfvhdlTeachable courseshttps://surf-vhdl.link/coursesMusic by Francis Preve - https://www.francispreve.com
Even if the VHDL is not a software language, we can find a tyoica SW statement, the iterative statement. Let’s see how to use thishttps://t.me/SurfVhdl/92Websitehttps://surf-vhdl.comTelegram channelhttps://t.me/SurfVhdlYou can contact memail: podcast@surf-vhdl.comTelegram: https://t.me/francesco_surfvhdlTeachable courseshttps://surf-vhdl.link/coursesMusic by Francis Preve - https://www.francispreve.com
Let’s understand how to implement a conditional statement in VHDLimage for the episodehttp://t.me/SurfVhdl/86Websitehttps://surf-vhdl.comTelegram channelhttps://t.me/SurfVhdlYou can contact memail: podcast@surf-vhdl.comTelegram: https://t.me/francesco_surfvhdlTeachable courseshttps://surf-vhdl.link/coursesMusic by Francis Preve - https://www.francispreve.com
Wait Statements in VHDLReference to pictures:https://t.me/SurfVhdl/82Websitehttps://surf-vhdl.comTelegram channelhttps://t.me/SurfVhdlYou can contact memail: podcast@surf-vhdl.comTelegram: https://t.me/francesco_surfvhdlTeachable courseshttps://surf-vhdl.link/coursesMusic by Francis Preve - https://www.francispreve.com
And now is time to introduce formally a Processlink to the imageshttps://t.me/SurfVhdl/78Websitehttps://surf-vhdl.comTelegram channelhttps://t.me/SurfVhdlYou can contact memail: podcast@surf-vhdl.comTelegram: https://t.me/francesco_surfvhdlTeachable courseshttps://surf-vhdl.link/coursesMusic by Francis Preve - https://www.francispreve.com
I receiver a question from Sandip. He got my reference, from my post on DDS.The question is:“I want to generate Square of 999kHz, 1000kHz and 1001kHzin VHDL Language and that would be implemented on a Zynq ZC702 evaluation board.Is it possible by using the DDS.? Can you provide your expertise and comment on it.”Websitehttps://surf-vhdl.comTelegram channelhttps://t.me/SurfVhdlYou can contact memail: podcast@surf-vhdl.comTelegram: https://t.me/francesco_surfvhdlTeachable courseshttps://surf-vhdl.link/coursesMusic by Francis Preve - https://www.francispreve.com
VHDL Packageshttp://t.me/SurfVhdl/74Websitehttps://surf-vhdl.comTelegram channelhttps://t.me/SurfVhdlYou can contact memail: podcast@surf-vhdl.comTelegram: https://t.me/francesco_surfvhdlTeachable courseshttps://surf-vhdl.link/coursesMusic by Francis Preve - https://www.francispreve.com
After signal introduction, let's view what are the remaining VHDL objectsImages https://t.me/SurfVhdl/72Websitehttps://surf-vhdl.comTelegram channelhttps://t.me/SurfVhdlYou can contact memail: podcast@surf-vhdl.comTelegram: https://t.me/francesco_surfvhdlTeachable courseshttps://surf-vhdl.link/coursesMusic by Francis Preve - https://www.francispreve.com
I received a question from Haitham. He have to connect a computer to an FPGA using USB connection in order to transfer data from FPGA to the PC. Haitham is following my VHDL course “Start Learning VHDL Using FPGA”. In this course the last LAB implement communication between PC and FPGA using UART channel.After starting the course, Haitham asked me: “Does the USB transfer work as UART”?Let’s see the answer. Here the link to the picture on the telegram channelhttps://t.me/SurfVhdl/68Websitehttps://surf-vhdl.comTelegram channelhttps://t.me/SurfVhdlYou can contact memail: podcast@surf-vhdl.comTelegram: https://t.me/francesco_surfvhdlTeachable courseshttps://surf-vhdl.link/coursesMusic by Francis Preve - https://www.francispreve.com
In this Q&A episode I want to answer to the question on what is the VHLD design flowTo better follow the episode, see the picture on the telegram channelhttps://t.me/SurfVhdl/65Websitehttps://surf-vhdl.comTelegram channelhttps://t.me/SurfVhdlYou can contact memail: podcast@surf-vhdl.comTelegram: https://t.me/francesco_surfvhdlTeachable courseshttps://surf-vhdl.link/coursesMusic by Francis Preve - https://www.francispreve.com
Introducing Flip-Flop in VHDLLink to the picture in the telegram channelhttps://t.me/SurfVhdl/61Websitehttps://surf-vhdl.comTelegram channelhttps://t.me/SurfVhdlYou can contact memail: podcast@surf-vhdl.comTelegram: https://t.me/francesco_surfvhdlTeachable courseshttps://surf-vhdl.link/coursesMusic by Francis Preve - https://www.francispreve.com
This is the question many of you ask me very oftenI wish to give you some hint and a test bench template I use in my VHDL designs Here the link to the test bench template: https://t.me/SurfVhdl/58Websitehttps://surf-vhdl.comTelegram channelhttps://t.me/SurfVhdlYou can contact memail: podcast@surf-vhdl.comTelegram: https://t.me/francesco_surfvhdlTeachable courseshttps://surf-vhdl.link/coursesMusic by Francis Preve - https://www.francispreve.com
A brief overview to setup a ModelSim simulation environmentLink to the episode#12 picturet.me/SurfVhdl/53Websitehttps://surf-vhdl.comTelegram channelhttps://t.me/SurfVhdlYou can contact memail: podcast@surf-vhdl.comTelegram: https://t.me/francesco_surfvhdlTeachable courseshttps://surf-vhdl.link/coursesMusic by Francis Preve - https://www.francispreve.com
Introduce signal in VHDL, what is a signal and how to use it.Image relative to this episodeWebsitehttps://surf-vhdl.comTelegram channelhttps://t.me/SurfVhdlYou can contact memail: podcast@surf-vhdl.comTelegram: https://t.me/francesco_surfvhdlTeachable courseshttps://surf-vhdl.link/coursesMusic by Francis Preve - https://www.francispreve.com
Solving a dispute in VHDL: the resolution functionLink to image for the episode#10Solving a dispute in VHDL: the resolution functiont.me/SurfVhdl/50Websitehttps://surf-vhdl.comTelegram channelhttps://t.me/SurfVhdlYou can contact memail: podcast@surf-vhdl.comTelegram: https://t.me/francesco_surfvhdlTeachable courseshttps://surf-vhdl.link/coursesMusic by Francis Preve - https://www.francispreve.com
What is a driver in VHDL?Images for the episodet.me/SurfVhdl/46Websitehttps://surf-vhdl.comTelegram channelhttps://t.me/SurfVhdlYou can contact memail: podcast@surf-vhdl.comTelegram: https://t.me/francesco_surfvhdlTeachable courseshttps://surf-vhdl.link/coursesMusic by Francis Preve - https://www.francispreve.com
Answering to Prashant. He asked me this question “What do we have to give as an input for i_clk and i_addr?”relative to the post: https://surf-vhdl.com/how-to-generate-sine-samples-in-vhdl/Websitehttps://surf-vhdl.comTelegram channelhttps://t.me/SurfVhdlYou can contact memail: podcast@surf-vhdl.comTelegram: https://t.me/francesco_surfvhdlTeachable courseshttps://surf-vhdl.link/coursesMusic by Francis Preve - https://www.francispreve.com/
In this episode we will introduce the Concurrency conceptWebsitehttps://surf-vhdl.comTelegram channelhttps://t.me/SurfVhdlYou can contact memail: podcast@surf-vhdl.comTelegram: https://t.me/francesco_surfvhdlTeachable courseshttps://surf-vhdl.link/coursesMusic by Francis Preve - https://www.francispreve.com
Introducing Entity. The basic building VHDL blockWebsitehttps://surf-vhdl.comTelegram channelhttps://t.me/SurfVhdlYou can contact memail: podcast@surf-vhdl.comTelegram: https://t.me/francesco_surfvhdlTeachable courseshttps://surf-vhdl.link/coursesMusic by Francis Preve - https://www.francispreve.com
Let’s understand how digital electronics help us in the debug and test of our designWebsitehttps://surf-vhdl.comTelegram channelhttps://t.me/SurfVhdlYou can contact memail: podcast@surf-vhdl.comTelegram: https://t.me/francesco_surfvhdlTeachable courseshttps://surf-vhdl.link/coursesMusic by Francis Preve - https://www.francispreve.com
Learn how men and women can be identified as digital circuitsWebsitehttps://surf-vhdl.comTelegram channelhttps://t.me/SurfVhdlYou can contact memail: podcast@surf-vhdl.comTelegram: https://t.me/francesco_surfvhdlTeachable courseshttps://surf-vhdl.link/coursesMusic by Francis Preve - https://www.francispreve.com/
Why do we use only two logic level in digital design?Figures:https://t.me/SurfVhdl/32Websitehttps://surf-vhdl.comTelegram channelhttps://t.me/SurfVhdlYou can contact memail: podcast@surf-vhdl.comTelegram: https://t.me/francesco_surfvhdlTeachable courseshttps://surf-vhdl.link/coursesMusic by Francis Preve - https://www.francispreve.com
Let's introduce the FLAT and Hierarchical methodology in Hardware DesignWebsitehttps://surf-vhdl.comTelegram channelhttps://t.me/SurfVhdlYou can contact memail: podcast@surf-vhdl.comTelegram: https://t.me/francesco_surfvhdlTeachable courseshttps://surf-vhdl.link/coursesMusic by Francis Preve - https://www.francispreve.com
Start understanding few rules for a good VHDL design habitsWebsitehttps://surf-vhdl.comTelegram channelhttps://t.me/SurfVhdlYou can contact memail: podcast@surf-vhdl.comTelegram: https://t.me/francesco_surfvhdlTeachable courseshttps://surf-vhdl.link/coursesMusic by Francis Preve - https://www.francispreve.com
Do you like digital electronic? Why you should learn VHDL? Let's understand in this episodeWebsitehttps://surf-vhdl.comTelegram channelhttps://t.me/SurfVhdlYou can contact memail: podcast@surf-vhdl.comTelegram: https://t.me/francesco_surfvhdlTeachable courseshttps://surf-vhdl.link/coursesMusic by Francis Preve - https://www.francispreve.com