Podcasts about verilog

Satnam Singh has got incredible experience in both academia and industry. He has worked in Google, Facebook, Microsoft, Microsoft Research, Xilinx, etc. He has been a lecturer in Glasgow, Birmingham and University of California for a couple of years. He has worked with many interesting tools such Coq, Haskell, Verilog, Tensorflow. These days he works at Groq, applying FP to design silicon for machine learning. In this episode we talk about the value of specification, the current state of academia, gaming the metrics, functional programming in hardware, bullying, among other things. Links Personal Website Satnam's X Groq

Uri Shaked surprises us with a chat about silicon design when we were expecting to talk about a web-based board simulator.  If you want to try your hand at silicon design, check out Tiny Tapeout, a way to possibly get your design on to real silicon. The digital design guide is a great way to start looking at how chips work. If you aren't quite ready for silicon, Wokwi has a Verilog simulator where you can learn to do the digital design. The Verilog Simon Game on Wokwi is amazing.  Wokwi is a web-Based simulator, simulating processors, boards, and peripherals. You can build a whole system there, from Dancing Servos to 7-Segment display from 30  LCDs and Arduino Mega to Raspberry Pi Pico boards you can program in C when you click More Options on the front page. You can also create your own peripheral using the Chip API. Or learn to use Zephyr on Wokwi. And now there is Wokwi for VS Code.  All that and Wokwi is open source: github.com/urish Uri recommends reading Relax for the same result by Derek Sivers Previously on Embedded 396: Untangle the Mess Transcript

https://arxiv.org/abs/2305.13243 00:00 Intro 01:21 Hardware security 02:54 How long have they been using AI to generate Verilog 05:26 Methodology 17:40 Humans in the loop 21:21 Some designs already taped out on TinyTapeout 3 26:49 How to contact

One big question is: How did the intelligence come into the FPGA? Therefore we discuss in today's episode two programming languages. Content of this Episode: * Programming languages * Verilog * VHDL * Graphic input * HLS = High Level Synthesis The World of FPGA is opening on the 14th of march. Follow us on LinkedIn to get all news and also come into our pre-opening newsletter. The post WFP007 – Programming languages for FPGAs appeared first on World of FPGA by David Kirchner.

בפרק הראשון דיברנו על מחזור החיים של צ'יפ ועל תפקידים לאורכו שדואגים לפתח אותו. אחד התפקידים הוא ה-Frontend Engineer.במה Frontend Engineer עוסק? מה הקשיים בפיתוח קוד חומרה?איך נראה היום-יום של מהנדס Frontend? איך אני יודע האם אני מתאים לתפקיד ולאן אני אוכל להתפתח בהמשך?כדי לענות על השאלות האלו, אירחנו את אמנון זיידמן וראיינו אותו על הקריירה שלו.שמענו מסלול לא שגרתי ומרתק עבור מהנדס חשמל, על הניסיון האדיר שצבר ועל הטכנולוגיה של Thunderbolt שהוא היה מעורב בתהליך הפיתוח שלה ואתם נהנים ממנה כיום.

Dinesh Tadepalli - Co-founder of incrEDIBLEspoon.com, Angel Investor and SoC Engineer by profession. As a Founder - Crazy enough to save the Planet, found the best alternatives and now expanding their presence across the world. Our planet, our responsibility. Did you eat your spoon today?As an Engineer - Love to work smart. Good at time/work management.Exponential passion for technology and products.A hardcore implementation and design engineer related to SOC Integration, Implementation, Netlisting, Synthesis, ECO, STA, Sign-off and Verilog modeling.Support the show

Zum Abschluss dieser Themenreihe spreche ich mit einem leitenden FPGA Entwickler aus Down Under, genauer aus Australien. Inhalt der Folge: * Interview mit Glenn Kirilow * Sein Weg zum FPGA Entwickler * VHDL oder Verilog in Australien * Unterschiede in der Ausbildung * Lernplattform TheEEView Der Beitrag IF172 – FPGA Down Under – Interview mit Glenn Kirilow erschien zuerst auf Ingenieurbüro David C. Kirchner.

Jetzt kennen wir die FPGAs aus den letzten Folgen schon recht gut, so dass ich heute noch einen kurzen Einblick geben möchte, wie die Funktion in die FPGAs kommt und wie diese Sprachen eingesetzt werden. Inhalt der Folge: * Programmier- vs. Beschreibungssprache * Verilog * VHDL * Gemeinsamkeiten * "Geheime" IP Blöcke * Grafische Eingabe * High-Level Synthesis Der Beitrag IF170 – Programmiersprachen für FPGAs erschien zuerst auf Ingenieurbüro David C. Kirchner.

This week, Marissa met with Sixto Cabrera, USU alum and Senior Electrical Engineer at Vivint. Join them as they discuss Sixto's unique educational timeline, a day in the life of an electrical engineer, setting healthy work boundaries in a high-demand job, and examples of Sixto's most meaningful work. Sixto is an experienced electronics engineer with professional experience in hardware design for a wide range of applications including embedded, IoT, RF, digital/analog circuits, and power electronics. He also has skills in programming/scripting languages such as C and C++, Python, R, MATLAB and Verilog. He is currently working as a Senior Electrical Engineer at Vivint. Learn more about and connect with Sixto by visiting his LinkedIn profile.

You may have played capture the flag as a kid, but did you know it's a term that also applies to cybersecurity? Capture the flag (CTF) events ask teams to hack into devices in order to detect vulnerabilities, and in this episode of Cyber Security Inside, Camille Morhardt gets into the details with award-winning academics Ahmad-Reza Sadeghi, who is a professor at TU Darmstadt in Germany, and JV Rajendran, who is an assistant professor at Texas A&M; both are steeped in hardware security knowledge and research, and they demonstrate why CTF events are such a great intersection of industry and academia. A fascinating discussion that you should definitely check out.   We cover: -  The meaning and history of “capture the flag” (CTF) in the digital realm, especially as it applies to hardware security -  The structure of a CTF event and the kinds of tools and resources made available to participating teams -  How people are trained to look for vulnerabilities, and how they might look for those even without a CTF event - The various classes of vulnerabilities, and why the trend of replicating them exists in the first place -  How the pandemic has impacted CTF ... and more.  Tune in!   The views and opinions expressed are those of the guests and author and do not necessarily reflect the official policy or position of Intel Corporation.   Here are some key take-aways: -  The purpose of capture the flag events is for great minds around the world to use their hacking skills to detect vulnerabilities that have purposefully been injected with bugs; that way, product security can be improved based on the findings. -  Similar to the children's game, CTF events are competitive; they're all about picking up “digital flags”, trying to outscore competitors along the way. -  CTF participants report back to judges to claim their points at the end of an event, and the results are then used to boost existing and future product security. -  A fantastic outcome of CTF events is that they sometimes lead to the discovery of new vulnerabilities on top of those that have been injected into the codes at hand. -  In addition to CTF events, academia is key in training students what to look for when detecting vulnerabilities in hardware. -  When selecting devices to experimentally hack into, it's important to consider the popularity of the device, as well as the device's ability to connect to other devices.   Some interesting quotes from today's episode: “That's the beauty of the human mind - you can run a lot of artificial intelligence, but nobody has these flashy ideas that come to the human brain.” “If a device exceeds a certain popularity, that means more people are using it, so we buy this device, and we hack into it.” “Jason Fung from Intel came to us and said, ‘Hey, I want to have a discussion with you.' He was pitching this idea of running the Capture the Flag competitions where he would provide buggy Verilog code, and ask students to find the bugs in the code and start exploiting them. And this was immediately great for me because I was looking for buggy Verilog code, and this guy from Intel comes and says he can provide that. And that's great, not just for training students, but also for my research. So that's how I got attracted to this line of work.”   “Sometimes they even find errors and vulnerabilities that we didn't inject into the code that we sent them. That's also the most important part of it. New vulnerabilities that teams find.”    “There are certain bugs that are more severe. That can be, as I said, remotely exploited even by an attacker who doesn't have the right privileges. Those kinds of attacks are far more serious. And our judges tend to value those attacks a lot more.”   “We cannot put it on a commercial platform because companies would not provide that. But this open source platform, on the other hand, is a good vehicle.”   “That has been a big influence, even for our research, because now we know like, ‘Hey, these are the bugs and the problems that the companies care about. So let's use those things to actually kind of reflect the real world scenario'.”   “Our lab aims to develop techniques to protect the designs against these kinds of attacks.”   “We do a kind of market research. If the device exceeds a certain popularity, that means more people are using it, so we buy this device, and we hack into it.”

Kuantum Teknolojileri Sohbetlerinin bu bölümünde doktorasını EPFL'de almış olan ve şu an ETH Zurich'teki Quantum Engineering Center'da çalışmalarını sürdüren Dr. Kadir Akın'ı konuk ettik. Kendisiyle ETH'daki 'quantum engineering' master programı ve FPGA'in quantum teknolojileri içerisinde kullanımı hakkında konuştuk. İsviçre'ye doktora için başvuru süreci hakkında bilgiler edindik ve Türkiye'deki üniversitelerin genel durumu hakkında sohbet ettik. Bu videoda yer alanlar: Dr. Kadir Akın - Quantum Engineering Center ETH Zurich Ecem Nur Duman - Yeditepe Üniversitesi Fizik Bölümü - Lisans Öğrencisi Zeki Seskir - ODTÜ Fizik Doktora Adayı ETH - Master in Quantum Engineering: https://master-qe.ethz.ch/ Kuantum Teknolojileri Sohbetleri #24 - 13.02.2021 - Bahadır Dönmez (Master in Quantum Engineering programında öğrenci) - https://www.youtube.com/watch?v=fBoSmCezFzs FPGA - https://en.wikipedia.org/wiki/Field-programmable_gate_array Verilog - https://en.wikipedia.org/wiki/Verilog

Fredrik chats with Wilson Snyder about Verilator, chip design, performance, and open hardware. This episode is a bit of a follow-up to episode 389 where Robert Wikandertalked - in Swedish - about verification of circuit designs. Afterward, Robert mentioned that we should really ask Wilson Snyder to talk about Verilator, and here we are! Wilson works with CPU and other hardware design, and is one of the lead developers of Verilator. When you design hardware, hardware description languages come in handy - you use them to describe hardware precisely. Then you can generate runnable code simulating the hardware, and run batteries of tests against it without needing to manufacture physical hardware. Verilator is one tool for turning code in the Verilog hardware description language into C++ or Systemc. The major competing tools are more on the interpreter side - which means that Verilator usually has a performance advantage. Oh, and it’s GPL licensed as well. As we discuss, Verilator doesn’t actually support all of Verilog, but that’s being worked on. And increased performance in itself is a clear goal of both research and concrete improvements. We also discuss a bit what might come out hardware-wise in the future. Wilson predicts DPUs - data-offload units, basically - will become even more of a thing than today. The second part of the discussion is focused on Verilator itself - how it’s built, designed, and developed. People with knowledge of compilers will feel right at home inside the Verilator source code. Thank you Cloudnet for sponsoring our VPS! Comments, questions or tips? We are @kodsnack, @tobiashieta, @oferlundand @bjoreman on Twitter, have a page on Facebook and can be emailed at info@kodsnack.se if you want to write longer. We read everything we receive. If you enjoy Kodsnack we would love a review in iTunes! You can also support the podcast by buying us a coffee (or two!) through Ko-fi. Links Wilson Snyder Robert Wikander - appeared in episode 389 (in Swedish) Digital equipment Verilator Hardware verification Synthesis - converting the language used into hardware gates Emacs Linus - yes, Torvalds GPL 2 GPL 3 Compiler Interpreter CHIPS alliance Duane Galbi got Verilator open sourced Tarball Systemc EDA - Electronic design automation Cadence Synopsys - provides synthesis tools Git RISC-V Open cores FPGA Open source ARM and MIPS cores Standard cell DSP Amiga ML GPUs DPUs Parsing Lexing Verilator on Github Verilator’s Github issues UVM - Universal verification methodology veripool.org Titles An open source tool that could do verification It started as a hobby It has a life of its own Into actual hardware gates Matching the languages A good escape story It’s bascially a compiler Open source hardware design The performance to generate the next CPU Innovation feedback cycles Download a core Always a little bit of a focus My real job is CPU design

Fredrik chats with Wilson Snyder about Verilator, chip design, performance, and open hardware. This episode is a bit of a follow-up to episode 389 where Robert Wikander talked - in Swedish - about verification of circuit designs. Afterward, Robert mentioned that we should really ask Wilson Snyder to talk about Verilator, and here we are! Wilson works with CPU and other hardware design, and is one of the lead developers of Verilator. When you design hardware, hardware description languages come in handy - you use them to describe hardware precisely. Then you can generate runnable code simulating the hardware, and run batteries of tests against it without needing to manufacture physical hardware. Verilator is one tool for turning code in the Verilog hardware description language into C++ or Systemc. The major competing tools are more on the interpreter side - which means that Verilator usually has a performance advantage. Oh, and it’s GPL licensed as well. As we discuss, Verilator doesn’t actually support all of Verilog, but that’s being worked on. And increased performance in itself is a clear goal of both research and concrete improvements. We also discuss a bit what might come out hardware-wise in the future. Wilson predicts DPUs - data-offload units, basically - will become even more of a thing than today. The second part of the discussion is focused on Verilator itself - how it’s built, designed, and developed. People with knowledge of compilers will feel right at home inside the Verilator source code. Thank you Cloudnet for sponsoring our VPS! Comments, questions or tips? We are @kodsnack, @tobiashieta, @oferlund and @bjoreman on Twitter, have a page on Facebook and can be emailed at info@kodsnack.se if you want to write longer. We read everything we receive. If you enjoy Kodsnack we would love a review in iTunes! You can also support the podcast by buying us a coffee (or two!) through Ko-fi. Links Wilson Snyder Robert Wikander - appeared in episode 389 (in Swedish) Digital equipment Verilator Hardware verification Synthesis - converting the language used into hardware gates Emacs Linus - yes, Torvalds GPL 2 GPL 3 Compiler Interpreter CHIPS alliance Duane Galbi got Verilator open sourced Tarball Systemc EDA - Electronic design automation Cadence Synopsys - provides synthesis tools Git RISC-V Open cores FPGA Open source ARM and MIPS cores Standard cell DSP Amiga ML GPUs DPUs Parsing Lexing Verilator on Github Verilator’s Github issues UVM - Universal verification methodology veripool.org Titles An open source tool that could do verification It started as a hobby It has a life of its own Into actual hardware gates Matching the languages A good escape story It’s bascially a compiler Open source hardware design The performance to generate the next CPU Innovation feedback cycles Download a core Always a little bit of a focus My real job is CPU design

When you're launching the next Falcon rocket or Mars rover, the last thing you want is one line of Verilog standing between you and a successful test. Sandip Dasgupta, Senior Electrical Engineer at SpaceX talks about smart rockets, FPGA design, and where SpaceX gets its ICs in this episode of Moore's Lobby.

In this week's episode, Dr. Ashish Darbari talks to Simon Davidmann - Founder & CEO of Imperas. Simon talks about his journey from being an inquisitive child to becoming the CEO of Imperas. His many influences on our industry include Verilog, SystemVerilog, and the fascinating work being done at Imperas in creating simulators for multiple different processor families, including Arm, RISC-V, and MIPS. Thank you, Simon Davidmann, for taking the time out to talk to us.     SHOW LESS          

Hackaday Editors Mike Szczys and Elliot Williams cover the most interesting hacks over the past week. So much talk of putting computers in touch with our brains has us skeptical on both tech and timeline. We celebrated the 40th Anniversary of the Walkman, but the headphones are the real star. Plus, Verilog isn't just for FPGAs, you can synthesize 7400 circuits too! Elliot is enamored by a subtractive printing process that uses particle board, and we discuss a couple of takes on hybrid-powered drones. Show Notes: https://hackaday.com/?p=368984

Die Kurzschluss Junkies sind unterwegs und reden mit Raphael und Dominik über Ihre Erfahrungen als Berufseinsteiger, persönliche Interessen, Projekte und Weiterbildung. Dominik empfiehlt für kapazitive Touch-Anwendungen einen PSoC von Cypress. Für eine 1-Button Lösung hat er den AT42QT1012 ausgewählt. Dieser benötigt keine Software um einen Touch Button zu realisieren. Außerdem weist er darauf hin , dass eine Ground-Plane auf dem Board besser gehatched wird, also die Kupfermasse der Plane zu reduzieren. So erhält man eine gute Schirmwirkung, ohne die Signalstärke zu sehr zu bedämpfen. Raphael empfiehlt für FPGA-Entwicklung Evaluation Boards von Digilent (bei Amazon) und Terasic. Weiterhin erzählt er von den verschiedenen Toolchains und die Eigenheiten von Verilog und VHDL. Bei opencores.org gibt's viele Beispiele von denen man lernen kann. Dominik und Raphael erzählen von den Erfahrungen als Berufseinsteiger und wie sie gelernt haben nach dem Studium Elektronik zu entwickeln. Sie geben Tipps, wie man mit dem Gefühl umgeht, keine Ahnung zu haben und wann man aufstehen und sagen soll: "Keine Ahnung, kann ich nicht." Zur Weiterentwicklung nutzen wir alle das Internet, Bücher und auch Schulungen. Aber im Endeffekt ist alles Learning by Doing. Das Entwickeln von Hardware ist eine Mischung aus Wissen, Erfahrung, Interesse und Black Magic. Natürlich haben wir auch über private Projekte gesprochen. Raphael entwickelt gerade eine Löt-Station für Weller RT Lötspitzen. Der Grund dafür ist ein Elektor Artikel, der ihm negativ aufgefallen ist. Seine Station bekommt den STM32F103 als Mikrocontroller, hat mehrere Varianten für die Strommessungen, ein Display und eine Schnittstelle für Erweiterungen. Die Dokumentation wird dann HIER zu finden sein, wenn er damit mal angefangen hat. (Wenn da noch kein Link ist, hat er noch nicht angefangen) Dominik beschäftigt sich mit Word-Clocks. Er hat da schon einige gebaut, jetzt gerade baut er eine Armbanduhr-Variante mit Alu Gehäuse und super kleinen Bauteilen. Zum Schluss erzählt Raphael von seiner Zeit als Werksstudent in der ASIC-Entwicklung.

Al Williams and the One Instruction WonderAl Williams One of the authors behind Hackaday, a website that features electronic projects and other things that appeal to people interested in computers, electronics, and technologyHam radio operatorAuthor of many booksHas worked on everything from underwater technology to the International Space Station and just about everything in betweenWas on previous episodesEP#57: Mr. Williams, your book changed my lifeEP#94: Al Williams and the Field Programmable Gate ArraysFPGA bootcamps on Hackaday5 out now, 6 soonFPGA development boardsUpduino Max10 ArrowDigilentiCEstickDr. DobbsThe One Instruction WonderA Universal Cross AssemblerThe Commando Forth CompilerWrite 8-bit code in your browserAtari 2600 programming in browser with simulation!Verilog compiler for designing a 8-bit platform from scratchJone's forth compiler: JONESFORTHProject JupyterIPython Interactive ComputingThe Jupyter NotebookSpace suit decompresses in outer spaceVisit our Public Slack Channel and join the conversation in between episodes!

Yay, after one year we're still polluting the virtual airwaves, so let's review the last year of podcasting (only takes about 8 minutes - don't cry). RetroChallenge RC2018/09 has finished, so we take a look at its winners and honourable mentions. Minor topics include a Hackalot visit, USB nullmodem hack, breadboard fail and fried scope probe clip. I briefly tried to generate a VGA image from software, but why not do it using an FPGA next time? Following convo deals with my initial experience with the Lattice ICEstick (iCE40HX1K) FPGA devboard, supported by a completely open toolchain (Yosys, Arachne-PNR, IceStorm). The J1(a) CPU is a small Forth-aimed CPU in Verilog, which leads yours truly into the weird and wonderful world of the Forth programming language. RetroChallenge 2018/09 contestants and final results Hackalot hackspace (.nl, text in Dutch) iCE40 FPGA: Lattice iCEstick USB FPGA devboard (iCE40HX1K) Yosys RTL synthesis tool for Xilinx 7 and Lattice iCE40 Arachne-PNR place & route tool for Lattice iCE40 IceStorm bitstream manipulation tools for Lattice iCE40 iCE40 FPGA & Forth: Swapforth for the J1a CPU and other platforms Swapforth explicitly for the J1a CPU Swapforth reference targeted at iCEstick, including memory map and peripheral access Forth: Gforth manual (HTML) or in PDF format - EXCELLENT Thinking Forth book by Leo Brodie Starting Forth by Leo Brodie (PDF), or in HTML format Programming Forth by Stephen Pelc HCC Retro division (in Dutch) - seems a bit outdated perhaps Nullmodem hack using homebrew module: Lame VGA image: Fancy VGA adapter:  

Vom 10. - 13. Mai 2018 fand im ZKM und in der Hochschule für Gestaltung (HfG) die GPN18 statt. Dort traf sich Sebastian mit Dennis Gnad, um mit ihm über Seitenangriffe auf Field Programmable Gate Arrays (FPGA) zu sprechen. FPGAs sind veränderliche Computerchips, die hervorragend bei der Entwicklung von logischen Schaltkreisen oder spezieller Glue Logic helfen, und kommen inzwischen auch als Rechenbeschleuniger zum Einsatz. Man kann FPGAs als Vorstufe zu Application-Specific Integrated Circuits (ASIC) sehen, auf denen Strukturen noch viel feiner, für höhere Taktraten und sparsamer abgebildet werden können, das Design aber um Größenordnungen teurer ist. Und während einem ASIC die Funktion ab Werk einbelichtet ist, können FPGAs nahezu beliebig oft zur Laufzeit umprogrammiert werden. Wie im Podcast zu digitalen Währungen erwähnt, spielen Graphical Process Units (GPUs), FPGAs und ASICs eine große Rolle bei Kryptowährungen. Hier ist ein einzelner FPGA-Chip beim so genannten Mining meisst nicht schneller als eine GPU, verbrauchen jedoch im Vergleich deutlich weniger Strom. Spezialisierte ASICs hingegen übersteigen in Effizienz und Geschwindigkeit alle anderen Lösungen. FPGAs finden sich aktuell in vielen Consumer-Produkten, wie dem Apple iPhone 7, im Samsung Galaxy S5, Smart-TVs und selbst auch der Pebble Smartwatch. Ihren besonderen Vorteil spielen FPGAs bei der Verarbeitung von großen Datenmengen wie Videodaten aus, da sie in der Parallelisierung nur durch den verfügbaren Platz beschränkt sind. Die Beschreibung von FPGAs und ASICs, oder deren Programmierung, erfolgt eher strukturell in Hardwarebeschreibungssprachen wie Verilog oder VHDL. Diese Beschreibungen unterscheiden sich sehr von imperativen Programmiersprachen, wie sie oft für CPUs oder GPUs verwendet werden. Es werden in logischen oder kombinatorischen Blöcken Daten verarbeitet, die dann in Taktschritten von und in Datenregister übertragen werden. Die erreichbare Taktfrequenz hängt von der Komplexität der kombinatorischen Blöcke ab. Ein Beispiel für logische Blöcke können Soft-Cores sein, wo zukünftige oder nicht mehr erhältliche CPU-Designs in FPGAs zur Evaluation oder Rekonstruktion abgebildet werden. Eine Variante ist die Entwicklung in OpenCL, wo verschiedene Architekturen wie GPUs, CPUs und FPGA unterstützt werden. Für die effiziente Umsetzung ist dafür weiterhin großes Hardwarewissen erforderlich, und man kann nicht erwarten, dass Code für FPGAs ebenso auf GPU, oder umgekehrt CPU-Code in FPGAs darstellbar ist. Das Interesse von Dennis Gnad liegt bei den FPGAs darin, deren Daten, Logik oder Inhalte durch Seitenkanalangriffe in von den Entwicklern unvorhergesehener Art und Weise auszulesen. Ein Beispiel ist das Erkennen von Fernsehsendungen aus dem Stromverbrauch des Fernsehgeräts wie es auch schon im Podcast zu Smart Metern beschrieben wurde. Ebenso wurden schon Kryptoschlüssel aus Geräuschen einer CPU bestimmt. Mit Soundkarten kann man Funkuhren verstellen und auch Grafikkarten können als UKW-Sender verwendet werden. Die elektromagnetische Abstrahlung ist ein sehr klassischer Seitenkanal und ist als Van-Eck-Phreaking seit 1985 bekannt. Gerade wurden die Timing- und Speculative-Execution-Covered-Channel-Angriffe Spectre und Meltdown für einen großteil aktueller CPUs bekannt, die aktiv Seitenkanäle für verdeckten Informationszugriff nutzen. Normalerweise benötigen Power-Side-Angriffe, die den Stromverbrauch auswerten, physischen Zugang zum Gerät oder der Stromversorgung. Überraschenderweise ist es auf FPGAs hingegen möglich den Stromverbrauch anderer Schaltungsbestandteile rein durch Software zu bestimmen. Dazu werden FPGAs an der Grenze der Timing-Parameter betrieben, und statistisch die erfolgreiche Ausführung gemessen. Mit verschieden langen Pfaden können auch gleichzeitig die Zeitschranken verschieden stark belastet werden und damit gleichzeitig für mehrere Spannungsstufen ausgewertet werden. Damit kann der relative Spannungsverlauf kontinuierlich gemessen werden. Im Zuge seiner Forschung zu Voltage Fluctuations in FPGAs konnte Dennis Gnad die Qualität der Messungen nachweisen. Für die eigentliche Auswertung der Messungen werden hier die Verfahren der Differential Power Analysis verwendet, die nicht absolute Messungen, sondern mit relativen Messungen den Verlauf oder Unterschiede in den Verläufen statistisch analysieren. Speziell wurden mit dem Pearson Korrelations-Koeffizient verschiedene Schlüssel-Hypothesen mit modellierten Stromverläufen aufgestellt, um den Suchraum für einen kryptographischen AES-Schlüssel jeweils stückweise einzuschränken. Dafür musste die spezielle AES-Implementation auf dem FPGA bekannt sein, um entsprechende Leakage-Modelle für die Korrelationsauswertung aufstellen zu können. Insgesamt wurde so ein rein software-getriebener Angriff auf FPGAs demonstriert, der ohne sehr aufwändiges Code-Review-Verfahren, dessen Umsetzung bei VHDL ohnehin große Fragen aufwirft, kaum zu entdecken ist. Dennis betreibt die Forschung als Doktorand am Chair of Dependable Nano Computing (CDNC) am Karlsruher Institut für Technologie (KIT), deren Forschung besonders auf die Verlässlichkeit und auch der Sicherheit von Computersystemen abzielt. Die Forschungsarbeiten zu Seitenkanälen über den Stromverbrauch haben ebenso Anwendungen für die Zuverlässigkeit von den Systemen, da ebenso mit der Messung auch eine entsprechende Beeinflussung bis zur Erzeugung von Fehlerzuständen möglich wird, wie es von Dennis durch Fehlerzustände in der Stromversorgung zum Neustart von FPGAs demonstriert werden konnte. Mit Stuxnet wurde bekannt, dass auch Industrieanlagen mit Software zerstört werden konnten, es gab aber auch Computermonitore, die kreativ in neue Nutzungszustände gebracht wurden. Literatur und weiterführende Informationen D. Gnad: Seitenkanal-Angriffe innerhalb FPGA-Chips, Vortrag auf der GPN18, Karlsruhe, 2018. F. Schellenberg, D. Gnad, A. Moradi, M. Tahoori: An Inside Job: Remote Power Analysis Attacks on FPGAs, Cryptology ePrint Archive: Report 2018/012, Proceedings of Design, Automation & Test in Europe (DATE), 2018. D. Gnad, F. Oboril, M. Tahoori: Voltage Drop-based Fault Attacks on FPGAs using Valid Bitstreams, International Conference on Field-Programmable Logic and Applications (FPL), Belgium, 2017. A. Moradi, F.-X. Standaert: Moments-Correlating DPA, Cryptology ePrint Archive: Report 2014/409, Theory of Implementations workshop, 2016. P. Kocher, J. Jaffe, B. Jun, et al: Introduction to differential power analysis, J Cryptogr Eng 1: 5, 2011. E. Brier, C. Clavier, F. Olivier: Correlation power analysis with a leakage model, International workshop on cryptographic hardware and embedded systems. Springer, Berlin, Heidelberg, 2004. Cryptology ePrint Archive Search Portal Side Channel Cryptanalysis Lounge - Ruhr-Universität Bochum D. Gnad, F. Oboril, S. Kiamehr, M. Tahoori: An Experimental Evaluation and Analysis of Transient Voltage Fluctuations in FPGAs, in IEEE Transactions on Very Large Scale Integration Systems (TVLSI), 2018. F. Schellenberg, D. Gnad, A. Moradi, M. Tahoori: Remote Inter-Chip Power Analysis Side-Channel Attacks at Board-Level], In Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD), USA, 2018. (to appear Nov. '18) J. Krautter, D. Gnad, M. Tahoori: FPGAhammer: Remote Voltage Fault Attacks on Shared FPGAs, suitable for DFA on AES], in IACR Transactions on Cryptographic Hardware and Embedded Systems (TCHES), Vol.1, No.3, 2018. (to appear Sept. '18)Podcasts A.-L. Baecker, C. Schrimpe: Crypto for the Masses – Grundlagen, Request for Comments, Der RFC Podcast, Folge 15, 2018. M. Lösch, S. Ritterbusch: Smart Meter Gateway, Gespräch im Modellansatz Podcast, Folge 135, Fakultät für Mathematik, Karlsruher Institut für Technologie (KIT), 2017. S. Ritterbusch, G. Thäter: Digitale Währungen, Gespräch im Modellansatz Podcast, Folge 32, Fakultät für Mathematik, Karlsruher Institut für Technologie (KIT), 2014. B. Heinz, T. Pritlove: FPGA, CRE: Technik, Kultur, Gesellschaft, Folge 117, Metaebene Personal Media, 2009.GPN18 Special D. Gnad, S. Ritterbusch: FPGA Seitenkanäle, Gespräch im Modellansatz Podcast, Folge 177, Fakultät für Mathematik, Karlsruher Institut für Technologie (KIT), 2018. http://modellansatz.de/fpga-seitenkanaele B. Sieker, S. Ritterbusch: Flugunfälle, Gespräch im Modellansatz Podcast, Folge 175, Fakultät für Mathematik, Karlsruher Institut für Technologie (KIT), 2018. http://modellansatz.de/flugunfaelle A. Rick, S. Ritterbusch: Erdbebensicheres Bauen, Gespräch im Modellansatz Podcast, Folge 168, Fakultät für Mathematik, Karlsruher Institut für Technologie (KIT), 2018. http://modellansatz.de/erdbebensicheres-bauenGPN17 Special Sibyllinische Neuigkeiten: GPN17, Folge 4 im Podcast des CCC Essen, 2017. A. Rick, S. Ritterbusch: Bézier Stabwerke, Gespräch im Modellansatz Podcast, Folge 141, Fakultät für Mathematik, Karlsruher Institut für Technologie (KIT), 2017. http://modellansatz.de/bezier-stabwerke F. Magin, S. Ritterbusch: Automated Binary Analysis, Gespräch im Modellansatz Podcast, Folge 137, Fakultät für Mathematik, Karlsruher Institut für Technologie (KIT), 2017. http://modellansatz.de/binary-analyis M. Lösch, S. Ritterbusch: Smart Meter Gateway, Gespräch im Modellansatz Podcast, Folge 135, Fakultät für Mathematik, Karlsruher Institut für Technologie (KIT), 2017. http://modellansatz.de/smart-meterGPN16 Special A. Krause, S. Ritterbusch: Adiabatische Quantencomputer, Gespräch im Modellansatz Podcast Folge 105, Fakultät für Mathematik, Karlsruher Institut für Technologie (KIT), 2016. http://modellansatz.de/adiabatische-quantencomputer S. Ajuvo, S. Ritterbusch: Finanzen damalsTM, Gespräch im Modellansatz Podcast, Folge 97, Fakultät für Mathematik, Karlsruher Institut für Technologie (KIT), 2016. http://modellansatz.de/finanzen-damalstm M. Fürst, S. Ritterbusch: Probabilistische Robotik, Gespräch im Modellansatz Podcast, Folge 95, Fakultät für Mathematik, Karlsruher Institut für Technologie (KIT), 2016. http://modellansatz.de/probabilistische-robotik J. Breitner, S. Ritterbusch: Incredible Proof Machine, Gespräch im Modellansatz Podcast, Folge 78, Fakultät für Mathematik, Karlsruher Institut für Technologie (KIT), 2016. http://modellansatz.de/incredible-proof-machine

@DERDIVER -- LINKEDIN:   Recruiting Background:  Versed in technical terms specific to each industry including but not limited to Microsoft, Oracle, Cisco, Peoplesoft, SAS, SAP and hardware/software engineering positions. Experience recruiting: Software Engineers (C/C++, C#, .net) Systems Admin's, Platforms, SCCM, Linux Unix administrators, embedded & middleware, CDMA, 802.xx ), Systems Engineers ( Physical layer, MAC layer), Hardware Engineers ( ASIC, FPGA, VHDL, Verilog ), RF Network Engineers, Engineering support, Systems Test Engineers, QA engineers (Software and Hardware), Analysts ( financial, business, CM/DM, multiple software packages including SAP, Baun, Peoplesoft.  Clients have included CIA, NGA, NRO, DoD, DHS, EOP, NOAA, DoS and DOE. Virtual Sourcing and Recruiting Techniques with cold calling, database,and Boolean Internet searches.  

02:02 - Ray Hightower Introduction Twitter GitHub Blog WisdomGroup ChicagoRuby WindyCityRails WindyCityThings 03:22 - Parallella Raspberry Pi 05:39 - Web Developers and The Hardware World 12:38 - Does a hardware background inform software? 18:42 - Learning and Playing Verilog 22:22 - Concurrency and Parallelism The Most Energy Efficient Supercomputer on the Planet by Ray Hightower at Madison+ Ruby 2015 github.com/parallella/parallella-examples 32:48 - Getting Started with Parallella Parallella Quick Start Guide (with gotchas) COIK = Clear Only If Known parallella.org/forums 41:02 - Use Cases 42:38 - IoT (Internet of Things) HealthKit HomeKit WatchKit Picks Refactoring Ruby with Monads (Coraline) Ruby Rogues Episode #120: Book Club: Understanding Computation with Tom Stuart (Chuck) Learning to play the piano (Jessica) Mogo Portable Seat (Chuck) Rob Pike: Concurrency Is Not Parallelism (Ray) Designing and Building Parallel Programs by Ian Foster (Ray)

02:02 - Ray Hightower Introduction Twitter GitHub Blog WisdomGroup ChicagoRuby WindyCityRails WindyCityThings 03:22 - Parallella Raspberry Pi 05:39 - Web Developers and The Hardware World 12:38 - Does a hardware background inform software? 18:42 - Learning and Playing Verilog 22:22 - Concurrency and Parallelism The Most Energy Efficient Supercomputer on the Planet by Ray Hightower at Madison+ Ruby 2015 github.com/parallella/parallella-examples 32:48 - Getting Started with Parallella Parallella Quick Start Guide (with gotchas) COIK = Clear Only If Known parallella.org/forums 41:02 - Use Cases 42:38 - IoT (Internet of Things) HealthKit HomeKit WatchKit Picks Refactoring Ruby with Monads (Coraline) Ruby Rogues Episode #120: Book Club: Understanding Computation with Tom Stuart (Chuck) Learning to play the piano (Jessica) Mogo Portable Seat (Chuck) Rob Pike: Concurrency Is Not Parallelism (Ray) Designing and Building Parallel Programs by Ian Foster (Ray)

02:02 - Ray Hightower Introduction Twitter GitHub Blog WisdomGroup ChicagoRuby WindyCityRails WindyCityThings 03:22 - Parallella Raspberry Pi 05:39 - Web Developers and The Hardware World 12:38 - Does a hardware background inform software? 18:42 - Learning and Playing Verilog 22:22 - Concurrency and Parallelism The Most Energy Efficient Supercomputer on the Planet by Ray Hightower at Madison+ Ruby 2015 github.com/parallella/parallella-examples 32:48 - Getting Started with Parallella Parallella Quick Start Guide (with gotchas) COIK = Clear Only If Known parallella.org/forums 41:02 - Use Cases 42:38 - IoT (Internet of Things) HealthKit HomeKit WatchKit Picks Refactoring Ruby with Monads (Coraline) Ruby Rogues Episode #120: Book Club: Understanding Computation with Tom Stuart (Chuck) Learning to play the piano (Jessica) Mogo Portable Seat (Chuck) Rob Pike: Concurrency Is Not Parallelism (Ray) Designing and Building Parallel Programs by Ian Foster (Ray)